(a) Field of the Invention
The present invention relates to an active-matrix in-plane switching mode LCD panel, and more particularly, to an improvement of an active-matrix LCD (liquid crystal display) panel driven by an in-plane electric field.
(b) Description of the Related Art
LCD panels are generally categorized by the mode of the liquid crystal into a plurality of types including one driven by a perpendicular electric field, such as a TN-mode (twisted nematic mode) LCD panel. In this mode of the LCD panel, the orientations of the directors (axes) of the LC molecules are changed by application of a perpendicular electric field which is normal to the substrate surface, to thereby control the transparency thereof (or transmittance of light passing therethrough) for image display on the display panel. This mode of the LCD panel, however, has the drawback of a narrow viewing angle wherein the refractive index of the LC layer largely depends on the viewing angle for the LCD panel, because the directors of the LC molecules are oriented in the direction normal to the substrate surface during application of the drive voltage. Thus, this mode of the LCD panel is not suited for a variety of applications which require a wider viewing angle.
On the other hand, another mode of the LCD panel, known as an in-plane switching mode LCD panel, has a higher viewing angle and provides a higher image quality. In this mode of the LCD panel, the directors of the LC molecules are initially oriented in the direction parallel to the substrate surface and applied with the lateral (in-plane) electric field to be rotated in a plane parallel to the substrate surface for controlling the light transmittance. Thus, the in-plane switching mode LCD panel is extensively studied and developed in recent days. It is known that the wider viewing angle and the higher image quality result from the extremely small dependency of the change in the refractive index of the LC layer on the viewing angle.
FIG. 1 shows the LCD panel (or LCD panel assembly) of an in-plane switching mode LCD device in a front view. The LCD panel assembly includes a plurality of scanning lines 502 extending in a column direction and driven by an external driver, a plurality of video signal lines 103 extending in a row direction perpendicular to the scanning lines 502, a plurality common electrode lines 106 extending parallel to the scanning line 502, and a plurality of pixel elements arranged in a matrix and each defined by a pair of adjacent scanning lines 502 and a pair of adjacent video signal lines 103. Each pixel element includes a TFT (thin film transistor) 503 acting as a switching transistor and an associated pixel electrode 104 connected to the source of the TFT 503. The common electrode line 106 has a pair of branches acting as common electrode 106A for each pixel element and extending parallel to the pixel electrode 104. The voltage applied between the pixel electrode 104 and the common electrode 106A generates a lateral electric field or in-plane electric field in each pixel element parallel to the substrate surface.
Referring to Fig. FIG. 2 taken along line IIxe2x80x94II in FIG. 1, the LCD panel assembly, generally designated by numeral 300, includes a TFT panel 100 and a counter panel 200 sandwiching therebetween a LC layer 107. The TFT panel 100 includes a TFT glass substrate 102, and, for each pixel, the common electrode 106A formed thereon, the pixel electrode 104 and the video signal line 103 formed thereon with an intervention of a gate insulator film 130. The pixel electrodes 104 and the signal lines 103 are disposed on the TFT panel 100 alternately with each other and covered with a protective insulator film 110, on which a first orientation film 120 is formed by coating and rubbing. The first orientation film 120 has a function for determining the orientation of the LC molecules in the LC layer 107 in the vicinity of the orientation film 120.
The counter panel 200 includes a counter glass substrate 101, a shield film 203 formed on the inner surface of the counter glass substrate 101 and having an opening for each pixel, a color layer 142 formed on the counter glass substrate 101 at each opening, a planarizing film 202 formed on the color layer 142, and a second orientation film 202 formed on the planarizing film 202 by coating and rubbing. The direction of the rubbing in the second orientation film 202 is opposite to the direction of the rubbing in the first orientation film 120.
Between the TFT panel 100 and the counter panel 200 are disposed the LC layer 107 and ball spacers 302, the ball spacers 302 having a diameter for defining the distance or gap between the TFT panel 100 and the counter panel 200. A first polarizing film 145 is formed on the outer surface of the TFT glass substrate 102 so that the light transmission axis of the polarizing film 145 is perpendicular to the direction of the rubbing in the orientation film 120. A second polarizing film 143 is formed on the outer surface of the counter substrate 101 so that the light transmission axis of the polarizing film 143 is perpendicular to the light transmission axis of the first polarizing film 145.
FIG. 3 shows a schematic block diagram of the LCD device having the LCD panel (assembly) 300 of FIG. 1, wherein the LCD panel 300 is placed on a back light 400 and driven by a LCD driver 500. The LCD driver 500 supplies scanning signals, video signals and a potential for the common electrode line to the LCD panel 300.
FIG. 4 shows an equivalent circuit diagram of the LCD panel assembly of FIG. 1. The scanning signals, the video signals and the common electrode potential are supplied from the LCD driver 500 shown in FIG. 3 to the scanning lines G1 to Gn, video signal lines D1 to Dn and the common electrode line COM, respectively. The common electrode potential is controlled by a variable voltage source ECOM in the LCD driver.
When one of the scanning lines G1 to Gn assumes a higher potential, the TFTs of the pixel elements disposed in a corresponding row are turned on, whereby electric charge flows from the video signal lines D1 to Dn into the corresponding pixel electrodes P1. This generates a specific voltage between the common electrode line 106 and the corresponding pixel electrodes 104, thereby generating an electric field between the pixel electrode 104 and the common electrode 106A. As a result, a portion of the LCD layer 107 interposed between both the panels 100 and 200 and located between both the electrodes 104 and 106A as viewed perpendicular to the substrate surface rotates parallel to the substrate surface, whereby the electro-optics effect of the LCD layer 107 allows image display based on the video signals.
FIG. 5 shows the distribution of the electric field generated in the pixel. The capacitance involved between the pixel electrode 104 and the common electrode 106A is considered to include a first, LC layer capacitance CLC which depends on the orientation of the LC layer 107 and a second, storage capacitance CSC which is constant, although both the capacitances are difficult to be separated. The sum of the capacitances CLC and CSC or the total capacitance between both the electrodes 104 and 106A can be obtained by the following formula:                                           ∫            v            D                    ⁢                                    ∫              0                        ⁢                                                            E                  _                                ·                                  ⅆ                                      D                    _                                                              ⁢                              ⅆ                v                                                    =                              1            2                    ⁢                      (                                          C                Lc                            +                              C                SC                                      )                    ⁢                      V            2                                              (        1        )            
wherein the integration with respect to xe2x80x9cvxe2x80x9d is conducted in the entire area for the LCD panel assembly, and E, D and V denote the electric field vector, the electric displacement vector and the voltage between the pixel electrode 104 and the common electrode line 106, respectively.
As understood from formula (1), the total capacitance depends on the medium through which the electric lines of force pass and the number of such electric lines of force. In FIG. 5, the electric lines of force xe2x80x9caxe2x80x9d, xe2x80x9cbxe2x80x9d, xe2x80x9ccxe2x80x9d and xe2x80x9cdxe2x80x9d pass mainly the counter glass substrate 101, the color layer 142, the LC layer 107 and the TFT glass substrate 102, respectively.
The color layer 142 is made of one of three pigments defining three primary colors including red (R), green (G) and blue (B), and the respective color layers are arranged with a specific rule in the LCD panel assembly, as will be described later with reference to FIG. 10. It is to be noted that each pigment among the three pigments has a specific dielectric constant and a specific thickness denoted by xe2x80x9cdCxe2x80x9d in FIG. 5. If an anthraquinone family pigment is used for the red film and a copper phthalocyanine family pigment is used for the green and blue films, then the red, green and blue films assume dielectric constant of 3.3, 3.9 and 4.5, respectively. This means that the capacitance CSC depends on the color of the pixel itself. The color may also cause a difference around 0.2 to 0.5 xcexcm in the film thickness depending on the desired hue. Thus, the thickness xe2x80x9cdgxe2x80x9d of the LC layer 107 also depends on the color, and accordingly the capacitance CLC also depends on the color. In short, different colors provide different LC layer capacitances CLC and different storage capacitances CSC to the pixel elements.
FIG. 6 shows a sectional view taken along line VIxe2x80x94VI in FIG. 1, with an abbreviation of the counter panel 200. In the active-matrix LCD panel having TFT pixel elements, a parasitic gate-to-source capacitance Cgs is formed in the overlapping region between the scanning line 502 and the pixel electrode 104. FIG. 7 shows an equivalent circuit for the pixel element, wherein the gate-to-source capacitance Cgs between the scanning line 502 and the pixel electrode 104 as well as the LC layer capacitance CLC and the storage capacitance CSC between the pixel electrode 104 and the common electrode 106A is depicted.
Referring to FIG. 8 showing potential waveforms of the signals for the pixel element, when the scanning line 502 assumes a higher potential level, the potential of the pixel electrode 104 approaches the potential xe2x80x9cDxe2x80x9d of the video signal line 103 due to the accumulation of the electric charge thereon. If the potential of the scanning line 502 falls at this stage to turn off the TFT, the potential of the pixel electrode 104 slightly falls because the pixel electrode 104 follows the potential fall of the scanning line 502 due to the parasitic capacitance Cgs. This potential fall xcex94V is generally called feed-through voltage, which is obtained approximately by the following formula:                               Δ          ⁢                      xe2x80x83                    ⁢          V                =                                            C              GS                                                      C                GS                            +                              C                Lc                            +                              C                SC                                              ⁢                      (                                          V                gon                            -                              V                goff                                      )                                              (        2        )            
wherein Vgon and Vgoff are the higher potential level and the lower potential level, respectively, of the potential xe2x80x9cGxe2x80x9d of the scanning line 502.
In general, the LCD panel has a configuration such that an alternating voltage is applied between the common electrode 106A and the pixel electrode 104 if noted in a single pixel, the alternating voltage changing its polarity every frame period. Since the orientation of the LC layers 107 depends on the video signal which differs between pixels, the feed-through voltage xcex94V depends on the state of the pixel image ranging from white through dark to black colors. Thus, the common electrode line 106 is in general applied with a median voltage which is a central voltage between the highest level and the lowest level of the video signal, the central voltage allowing a highest sensitivity to eye and thereby preventing a flicker.
The feed-through voltage xcex94V obtained from equation (2) is in fact changed if the scanning signal xe2x80x9cGxe2x80x9d has a delay or do not have a sharp rise edge in the waveform thereof, as detailed below. If the scanning signal xe2x80x9cGxe2x80x9d has a delay, such as shown in FIG. 9A compared to the case of FIG. 9B which does not involve a delay, current flows into the pixel electrode 104 for a short time period after the instant at which the scanning signal xe2x80x9cGxe2x80x9d falls from a high level to a low level. The current continues to flow until the potential of the scanning signal xe2x80x9cGxe2x80x9d falls down to the threshold voltage Vth at which the TFT is turned off. Assuming that t0 and t1 are time instants at which the potential of the scanning signal xe2x80x9cGxe2x80x9d is switched from the high level to the low level and at which it actually falls down to the threshold voltage Vth, respectively, the feed-through voltage xcex94V in this case can be expressed as follows:                               Δ          ⁢                      xe2x80x83                    ⁢          V                =                                                            C                GS                                                              C                  GS                                +                                  C                  Lc                                +                                  C                  SC                                                      ⁢                          (                                                V                  gon                                -                                  V                  goff                                            )                                -                                    ∫              t0              t1                        ⁢                                                            I                  ⁡                                      (                    t                    )                                                                                        C                    GS                                    +                                      C                    LC                                    +                                      C                    SC                                                              ⁢                              ⅆ                t                                                                        (        3        )            
wherein I(t) is the current at a time instant xe2x80x9ctxe2x80x9d residing between the time instants t0 and t1.
It is to be noted that the scanning signal xe2x80x9cGxe2x80x9d has a larger delay at the distal end of the scanning line 502 as shown in FIG. 9A compared to the proximal end thereof as shown in FIG. 9B. Thus, the feed-through voltage xcex94V is larger at the pixels in the vicinity of the proximal end of the scanning line as shown in FIG. 9B compared to the pixels in the vicinity of the distal end thereof as shown in FIG. 9A.
As understood from formula (1), the total capacitance CLC+CSC depends on the medium through which the electric line of force passes. In the conventional in-plane switching mode LCD panel described above, since the counter panel 200 does not mount thereon transparent electrodes, the electric field generated between the pixel electrode and the common electrode enters the color layer 142. The difference in the film thickness and in the dielectric constant between the different color layers generates a difference in the field-through voltage xcex94V between the different color layers 142. Thus, if the potential of the common electrode line is adjusted to compensate the feed-through voltage for one of the three color layers to cancel the flicker, the flicker will appear in the pixels having the other two of the three color layers. The DC voltage component generating the flicker in the other two of the color layers also causes the burning, irregularity and stains in the pixels to degrade the reliability of the LCD panel.
In addition, as described before with reference to formula (3), the delay of the scanning signal causes the difference in the feed-through voltages xcex94V between pixels due to the difference in the time instant t1. This delay increases with the increase of the time constant of the scanning signal line, which increases with a higher resolution or the increase of the dimensions of the LCD panel. The time constant my be reduced to some extent by a larger width of the scanning signal line, which however decreases the ratio of the area for the opening to the entire pixel area and thus decreases the brightness of the screen or increases the power dissipation of the LCD panel, thereby degrading the performance of the LCD panel.
Patent Publication JP-A-5-224235 describes, in a LCD panel acting for a perpendicular electric field and thus not in an in-plane switching mode, a transparent common electrode mounted on the counter panel is divided into a plurality of common electrodes, and the divided common electrodes are applied with different potentials. However, a lower accuracy of the relative locations between the TFT panel and the counter panel necessitates a larger shield area between the pixels, and reduces the light transmittance.
In addition, division of the common electrode increases the patterning steps for the common electrode. It is to be noted that a fine patterning for the transparent electrode is difficult to achieve due to the material itself. The increase in the number of electric leads between the TFT panel and the counter panel complicates the fabrication process. In an in-plane switching mode LCD panel, the common electrode line formed on the TFT panel does not cause the problems of fine patterning or increase in the electric leads between the panels.
Some patent publications JP-A-8-211411, JP-A-10-62802, and WO96/00408 describe in-plane switching mode LCD devices wherein common electrode lines are applied with respective voltages. However, there is no teaching that teaches the application of respective voltages to the common electrode lines for the purpose of correction of the irregularity in the feed-through voltage of the pixels having different color layers, the irregularity being caused by the pulse delay of the scanning signal.
It is therefore an object of the present invention to provide a LCD panel generating a less flicker level and capable of reducing burning, irregularity and stains in the pixels.
The present invention provides a LCD panel assembly including a first panel, a second panel and a LCD layer sandwiched therebetween, the first panel including a first substrate, and a plurality of pixel elements arranged in a matrix on the first substrate and each including a TFT, a pixel electrode and a common electrode, the pixel electrode and the common electrode generating therebetween a lateral electric field parallel to a surface of the first substrate, a plurality of common electrode lines each connected to a corresponding common electrode, a plurality of scanning lines each disposed for a corresponding row of the pixel elements and connected to gates of the TFTs in the corresponding row, and a plurality of video signal lines each disposed for a corresponding column of the pixel elements and connected to source/drain paths of the TFTs in the corresponding column, the scanning lines form a plurality of groups each corresponding to the pixel elements having an equal total capacitance between the pixel electrode and the common electrode in the pixel element, each of the groups being applied with a separate voltage independently of voltages applied to other of the groups.
In accordance with the present invention, the groups of the common electrode lines can be applied with respective voltages so that the flicker level of the pixels connected to each group of the common electrode lines assumes a minimum by compensating the difference in the feed-through voltage between the pixels.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.